1. Field of the Invention
This invention relates generally to memory systems for electronic data processing systems and, in particular, to an improved bit-organized memory organization which provides an error-correctible RAM system.
2. Description of the Prior Art
In recent years data processing systems have been evolving towards more efficient and larger systems. Of critical importance to these data processing systems are their memory systems. Trends in the development of data processing systems have been paralleled, and significantly aided, by the development of very large memory systems.
Among the requirements for memory systems is need for extremely high accuracy. Since this requirement generally exceeds cost-effective solutions for providing error-free components and organizations, memory systems are generally provided with error-detection and correction (EDAC) subsystems. The detection part of an EDAC subsystem will detect the presence of errors within its associated memory system. However, the correction portion of the EDAC system is generally limited to correcting only those errors are one-bit per word. This means that multi-bit errors (an error occurring in more than one bit per word) can be detected but not corrected, and will result in the requirement for system overhead. System overhead may be in the form of other means to correct these errors (such as softwear or possibly result in shutting down the system until the errors can be isolated and corrected. Overhead is extremely costly and therefore it is highly desirable to minimize the cause of such an occurrence, namely, multi-bit errors.
Memory systems are typically comprised of semiconductor chips such as random access memories (RAMs). In general, there are three different causes of errors in a memory system:
1 FAULTY SEMICONDUCTOR MEMORY CHIPS,
2 FAULTS WITHIN ASSOCIATED MEMORY HARDWARE, AND
3 ERROR CAUSING FACTORS WITHIN THE MEMORY ENVIRONMENT.
The first gategory is self-explanatory. The second category includes faults within such associated circuitry as logic, drivers, receivers, etc. or various types of shorts (for example, those caused by loose solder or system vibration). The third category includes such factors as heat, atmospheric pressure, humidity or exposure to light. The present invention is directed to errors resulting from the first or second categories. Its affect is to limit errors caused by these factors to only one-bit per word and hence be error-correctible. In an appropriately designed system, such as that disclosed herein, this can have the overall effect of limiting approximately ninety percent of all memory errors to one-bit per word errors.